Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications

This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given. Up to what extent DeFinFET stands as a promising c...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2020-11, Vol.67 (11), p.4728-4735
Main Authors: Kumar, B. Sampath, Ajay, Paul, Milova, Somayaji, Jhnanesh, Gossner, Harald, Shrivastava, Mayank
Format: Article
Language:English
Subjects:
Circuit reliability
DeMOS
Drain-extended FinFET (DeFinFET)
drain-extended MOS
Electrostatic discharges
Energy conversion efficiency
FinFETs
Integrated circuit reliability
laterally double diffused MOS (LDMOS)
Logic gates
Nodes
Performance evaluation
Power amplifiers
PwrSoC
Radio frequency
Reliability analysis
SoC
System on chip
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Summary:This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given. Up to what extent DeFinFET stands as a promising choice is carefully investigated through device-circuit interactions and reliability analysis of range of DeFinFET options. The same is then compared, in terms of radio frequency (RF)-power amplifier (PA) performance, dc-dc conversion efficiency, electrostatic discharge (ESD) robustness, and hot carrier immunity (HCI) reliability, with other HV alternatives in FinFET nodes and its planar counterpart, that is drain-extended MOS (DeMOS).
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2020.3020904