Determination of Power MOSFET's Gate Oxide Degradation Under Different Electrical Stress Levels Based on Stress-Induced Oxide Capacitance Changes

• Published in: IEEE transactions on electron devices 2021-02, Vol.68 (2), p.688-696
• Main Authors: Sezgin-Ugranli, Hatice Gul, Ozcelep, Yasin
• Format: Article
• Language: English
• Subjects: Capacitance; Circuit design; circuit simulation; Curve fitting; Degradation; Diffusion effects; Field effect transistors; Integrated circuit modeling; Logic gates; Mathematical model; Mathematical models; Metal oxide semiconductors; modeling; MOSFETs; nonlinear circuits; power MOSFET; Semiconductor devices; SPICE; Stress; Voltage measurement
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.3044269

In this article, we aim to investigate the gate oxide degradation of power MOSFETs through oxide capacitance. We focus on modeling the oxide capacitance variation as a function of several stress levels and time intervals. The experimental procedure is carried out by means of commercial n-channel vertical double-diffused metal-oxide semiconductor field-effect transistors (VDMOSFETs) that have maximum voltage and current ratings as 200 V and 5.2A, respectively. We calculate the oxide capacitance using measurable reverse capacitance that is equal to gate-drain capacitance. The turn-around point is determined at each stress level. We observe that the oxide capacitance shows a nonlinear variation due to the stress time and level. The variation is divided into two regions for the model. The modeling procedure starts with the mathematical fitting. The equations are obtained by using curve fitting methods. The circuit model is designed via SPICE Simulation by using these equations. We also consider the turn-around points for the circuit design. The simulation and experimental results have good compatibility. We achieve 92.3% and 90.8% similarity on average for first and second region of the variation, respectively.