Synchronous Adaptive Resolver-to-Digital Converter for FPGA-Based High-Performance Control Loops

This paper deals with a gain scheduling synchronous demodulation scheme useful to obtain speed and position measurements from resolver position sensors. The proposed algorithm is devoted to a field-programmable gate array implementation in order to provide the elaborated information for very low lat...

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Bibliographic Details
Published in:IEEE transactions on instrumentation and measurement 2019-10, Vol.68 (10), p.3972-3982
Main Authors: Sabatini, Valerio, Di Benedetto, Marco, Lidozzi, Alessandro
Format: Article
Language:English
Subjects:
Adaptive control
Algorithms
Converters
Demodulation
Estimation
Excitation
Field programmable gate arrays
Field-programmable gate array (FPGA)
Frequency control
Gain scheduling
high-speed drives
Integrated circuits
Loops
Low speed
phase-locked loop
Position measurement
Position sensing
resolver-to-digital converter (RDC)
Resolvers
Sensor arrays
Signal resolution
Square waves
Velocity control
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Description
Summary:This paper deals with a gain scheduling synchronous demodulation scheme useful to obtain speed and position measurements from resolver position sensors. The proposed algorithm is devoted to a field-programmable gate array implementation in order to provide the elaborated information for very low latency control loops. The presented design allows getting accurate estimations in a wide range of rotational speeds without requiring costly off-the-shelf integrated circuits and leads to higher accuracy at low speed if compared to commercial solutions. To this purpose, the resolver excitation circuit has been simplified working directly with a square wave signal, and the resolver frequency behavior due to the nonsinusoidal excitation has been considered.
ISSN:0018-9456
1557-9662
DOI:10.1109/TIM.2018.2884556