A Scalable RFCMOS Noise Model

This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasin...

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Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2009-05, Vol.57 (5), p.1009-1019
Main Authors: Tong, A.F., Wei Meng Lim, Yeo, K.S., Choon Beng Sia, Wen Cong Zhou
Format: Article
Language:English
Subjects:
Applied sciences
BSIM3v3
Circuit design
Circuit noise
Circuit simulation
Computer simulation
Cycle time
Design
Design engineering
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Geometry
Hafnium
HF noise modeling
high-frequency (HF) noise model
Integrated circuits
Mathematical models
Microwaves
MOSFET circuits
Noise
Noise figure
Noise measurement
Radio frequency
RF MOSFET
RFCMOS
Scalability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Solid modeling
Studies
Verilog-A
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Description
Summary:This paper presents the high-frequency (HF) noise modeling of an RF MOSFET for a 90-nm technology node. A brief discussion on the noise measurement theory is presented to illustrate the limitation of the noise measurement system. The extracted noise sources were studied for their geometry and biasing dependences and by implementing additional noise sources into the small-signal RFCMOS model, accurate HF noise simulation for the transistor can be achieved. Verilog-A is used for the coding of the additional noise sources into the RFCMOS model and the added noise source will compensate the underestimation of the channel thermal noise from the BSIM3v3 core model. Simulated noise circles and the measured noise figures are plotted at other source impedances to show that all the noise parameters are simulated accurately. The biasing and geometry dependences of the measured and simulated noise parameters are presented to demonstrate the scalability of the developed HF noise model. The scalability feature in HF noise model can be implemented into the process design kit (PDK) so that more powerful PDK can be developed for the circuit designers to optimize and simulate their circuit design that requires stringent noise specifications. The accurate noise simulation can ensure better chance of success and reduce the number of tape-out and design cycle time.
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2009.2017245