Design of CMOS Power Amplifiers

This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals. We show that most important limitations arise from the limited breakdown voltage of...

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Bibliographic Details
Published in:IEEE transactions on microwave theory and techniques 2012-06, Vol.60 (6), p.1784-1796
Main Authors: Niknejad, A. M., Chowdhury, D., Jiashu Chen
Format: Article
Language:English
Subjects:
Amplitude modulation
Circuit design
CMOS
CMOS integrated circuits
CMOS power amplifier (PA)
CMOS RF PA
CMOS technology
Devices
digital PA
digital RF
Impedance
Inductors
Linearity
Logic gates
Nanostructure
Power amplifiers
Substrates
Transistors
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Summary:This paper describes the key technology and circuit design issues facing the design of an efficient linear RF CMOS power amplifier for modern communication standards incorporating high peak-to-average ratio signals. We show that most important limitations arise from the limited breakdown voltage of nanoscale CMOS devices and the large back-off requirements to achieve the required linearity, both of which result in poor average efficiency. Two fundamentally different approaches to tackle these problems are presented along with silicon prototype measurements. In the first approach, transformer power combining and bias-point optimization are used to increase the output power and linearity of the "analog" amplifier. In the second approach, a mixed-signal "digital" polar architecture is employed, wherein the amplitude modulation is formed through an RF DAC structure.
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2012.2193898