A Six-Phase Two-Stage Blocker-Tolerant Harmonic-Rejection Receiver

• Published in: IEEE transactions on microwave theory and techniques 2020-05, Vol.68 (5), p.1964-1976
• Main Authors: Ul Haq, Faizan, Englund, Mikko, Antonov, Yury, Tenhunen, Miikka, Stadius, Kari, Kosunen, Marko, Ostman, Kim B., Koli, Kimmo, Ryynanen, Jussi
• Format: Article
• Language: English
• Subjects: <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">N -path filtering; Baseband; Blocker resilience; Broadband; Clocks; direct downconversion receivers; Gain; Harmonic analysis; harmonic rejection (HR); Linearity; Mixers; Receivers; Rejection
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2020.2966152

Modern wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this article, we introduce a blocker-tolerant harmonic rejection (HR) receiver, which can suppress blockers at the local oscillator harmonics. The suppression is achieved by applying the HR in two stages, such that the first HR already occurs at the first gain-stage output. The proposed receiver achieves this HR with a simple six-phase local-oscillator (LO) clocking. The proposed design also uses simple gain coefficients of ±1 while implementing HR in two stages that compensates for the mismatch effects of each stage. In addition, the near-band blocker linearity is improved by implementing a third-order baseband feedback response, which acts in conjunction with the N -path filtering. Implemented in a 28-nm Fully-Depleted Silicon-on-Insulator (FDSOI) process, the receiver demonstrates the 18-37-dB HR from the first stage and 46-53 dB of HR in total. Furthermore, a blocker compression point (BCP) of 2.5 dBm for a third harmonic blocker and a near-band BCP of −6.5 dBm are achieved.