Exploring Fine-Grained Fault Tolerance for Nanotechnology Devices With the Recursive NanoBox Processor Grid

Advanced molecular nanotechnology devices are predicted to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We describe and evaluate the Recursive NanoBox Processor Grid as an application specific, fault-tolerant, paralle...

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Bibliographic Details
Published in:IEEE transactions on nanotechnology 2006-09, Vol.5 (5), p.575-586
Main Authors: KleinOsowski, A., Pai, V.V., Rangarajan, V., Ranganath, P., KleinOsowski, K., Subramony, M., Lilja, D.J.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit faults
Computer architecture
Computers, microcomputers
Design. Technologies. Operation analysis. Testing
Electronics
Error correction
Exact sciences and technology
Fabrication
Fault tolerance
Fault tolerant systems
Hardware
Hardware design languages
Integrated circuits
Integrated circuits by function (including memories and processors)
logic design
Mathematical models
Microprocessors
Molecular electronics, nanoelectronics
Nanocomposites
Nanomaterials
Nanoscale devices
Nanostructure
Nanotechnology
Nanotechnology devices
Parallel processing
Recursive
robustness
Semiconductor device modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Description
Summary:Advanced molecular nanotechnology devices are predicted to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We describe and evaluate the Recursive NanoBox Processor Grid as an application specific, fault-tolerant, parallel computing system designed for fabrication with unreliable nanotechnology devices. In this study we construct hardware description language models of a NanoBox Processor cell and evaluate the effectiveness of our recursive fault masking approach in the presence of random errors. Our analysis shows that complex circuits constructed with encoded lookup tables can operate correctly despite 2% of the nodes being in error. The circuits operate partially correct with up to 4% of the nodes being in error
ISSN:1536-125X
1941-0085
DOI:10.1109/TNANO.2006.880901