Fault Models for Logic Circuits in the Multigate Era

With increased scaling to lower technology nodes, the electrostatic integrity of planar FETs is expected to worsen, necessitating the adoption of low-leakage high-performance multigate FETs, amongst which the FinFET is very attractive with respect to fabrication process complexity. A significant voi...

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Bibliographic Details
Published in:IEEE transactions on nanotechnology 2012-01, Vol.11 (1), p.182-193
Main Authors: Bhoj, A. N., Simsir, M. O., Jha, N. K.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit faults
Circuit properties
Circuits
CMOS
CMOS integrated circuits
Computer simulation
Delay
Design. Technologies. Operation analysis. Testing
Device simulation
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Etching
Exact sciences and technology
fault models
Faults
FinFETs
Gates (circuits)
independent-gate structure
Integrated circuit modeling
Integrated circuits
Integrity
leakage
Logic gates
Semiconductor device modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductors
shorted-gate structure
Testing, measurement, noise and reliability
Transistors
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Summary:With increased scaling to lower technology nodes, the electrostatic integrity of planar FETs is expected to worsen, necessitating the adoption of low-leakage high-performance multigate FETs, amongst which the FinFET is very attractive with respect to fabrication process complexity. A significant void from a circuit testing viewpoint is the absence of fault models for FinFETs. In particular, it is unclear if CMOS fault models are comprehensive enough to model all defects in FinFET circuits. We investigate the aforementioned problem using mixed-mode FinFET device simulation and demonstrate that while faults defined for planar FETs show significant overlaps with FinFETs, they do not encompass all regimes of operation. Results indicate that no single fault model can adequately capture the leakage-delay behavior of logic gates based on independent-gate FinFETs with opens on the back gate, and shorted-gate FinFETs, which have been accidentally etched into independent-gate structures. To this effect, we categorize back-gate cuts into three regimes where either pulse broadening or pulse shrinking occurs, which can be tested using three-/two-pattern delay fault tests.
ISSN:1536-125X
1941-0085
DOI:10.1109/TNANO.2011.2169807