Fast and Energy-Efficient CNFET Adders With CDM and Sensitivity-Based Device-Circuit Co-Optimization

• Published in: IEEE transactions on nanotechnology 2018-07, Vol.17 (4), p.783-794
• Main Authors: Haghshenas, Kawsar, Hashemi, Mona, Nikoubin, Tooraj
• Format: Article
• Language: English
• Subjects: Adders; Carbon nanotube field effect transistor (CNFET); CDM methodology; CNTFETs; device-circuit co-optimization; Electron tubes; Energy efficiency; energy efficient circuit; Fabrication; full adder; Optimization; sensitivity based optimization; sizing algorithm
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2018.2834511

Since integrated circuit technology entered into the nanoscale regime, energy efficiency has become one of the most significant challenges. The carbon nanotube field effect transistor (CNFET) is one of the highly appreciated nanoscale devices for replacement due to its similar process to the current CMOS technology. The big question in this paper is what are the other specific controllable parameters in CNFET technology for designers to design high-performance and energy-efficient circuits and how much these parameters impact the circuit characteristics? In this regard, two energy-efficient full adders, as the crucial building blocks of digital systems, in 32 nm CNFET technology are designed. Cell design methodology as an efficient logic style is used for the new designs, and CNFET-SEA is used for the optimization. The CNFET-SEA, which is a modification of simple exact algorithm (SEA), is proposed as an appropriate sizing algorithm for circuits in CNFET technology. The sensitivity analysis, as a new approach, is used in the CNFET-SEA algorithm to obtain better sizing results in shorter runtime. The number of tubes, the diameter of tubes, and pitch are considered as the three specific device parameters in the CNFET technology for device-circuit co-optimization, and their effect on the circuit characteristics is investigated. The simulation results show a 15-97% delay, 8-87% power-delay product (PDP), and 22-99% energy-delay product improvement for the proposed full adders compared with the referenced ones. The PDP optimization with CNFET-SEA in comparison with SEA shows 11-20% improvement with a significant runtime reduction for selected adders.