1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation

• Published in: IEEE transactions on nanotechnology 2023-01, Vol.22, p.1-6
• Main Authors: Sk, Masud Rana, Thunder, Sunanda, Muller, Franz, Laleni, Nellie, Raffel, Yannick, Lederer, Maximilian, Pirro, Luca, Chohan, Talha, Hsuen, Jing-Hua, Wu, Tian-Li, Seidel, Konrad, Kampfe, Thomas, De, Sourav, Chakrabarti, Bhaswar
• Format: Article
• Language: English
• Subjects: 1/f noise; 1F-1T; Accuracy; Arrays; Computer architecture; Computer memory; Constraining; FeFET; FeFETs; Ferroelectricity; Field effect transistors; HfO<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> _{2}</tex-math> </inline-formula>; Logic gates; Mathematical analysis; Matrices (mathematics); Matrix algebra; Memory Array; Microprocessors; Multilayer perceptrons; Multilayers; Neural networks; Semiconductor devices; Simulation; Synapses; Transistors; Vector-matrix-multiplication; Vectors (mathematics)
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2023.3295093

This article proposes a memory cell, denoted by 1F-1T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (I_{d}) variations by limiting the on-state current in FeFET. The experimental data from our 28nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (I_{BL}) variation and the accuracy of vector-matrix multiplication of the 1F-1T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.