High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator for Image Processing and Neural Networks

• Published in: IEEE transactions on nanotechnology 2024, Vol.23, p.748-757
• Main Authors: Kaushik, Nandit, Srinivasu, B.
• Format: Article
• Language: English
• Subjects: Acceptable noise levels; adder; Adders; Artificial neural networks; Circuits; comparator; Comparators; Equivalence; Image processing; IMPLY; in-memory computing; Logic; MAGIC; memristor; Memristors; Motion perception; Network topology; Neural networks; Noise measurement; Signal to noise ratio; subtractor; Switches; Topology; Voltage
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2024.3487223

In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67× with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43×, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93× faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.