An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMS

A technique that will improve RAM cell performance while maintaining single event upset immunity has been identified. The resistor-hardening configuration combines cross-coupled gate resistors and a pair of resistors used to isolate the miore sensitive devices (those not fabricated in wells). Improv...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 1986-12, Vol.33 (6), p.1730-1733
Main Authors: Johnson, Richard L., Diehl, Sherra E.
Format: Article
Language:English
Subjects:
Applied sciences
Circuits
CMOS process
CMOS technology
Computer simulation
Energy
Energy. Thermal use of fuels
Exact sciences and technology
Feedback
Fission nuclear power plants
Installations for energy generation and conversion: thermal and electrical energy
Radiation hardening
Random access memory
Read-write memory
Resistors
Single event upset
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A technique that will improve RAM cell performance while maintaining single event upset immunity has been identified. The resistor-hardening configuration combines cross-coupled gate resistors and a pair of resistors used to isolate the miore sensitive devices (those not fabricated in wells). Improvements in RAM cell write time and critical charge are discussed as well as the impact of this technique on the cell's noise miargin.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1986.4334679