Effectiveness of CMOS Charge Reflection Barriers in Space Radiation Environments

Single event upsets in microelectronic circuits follow the collection of more than some critical amount of charge at certain reverse-biased junctions. Reducing charge collection at the junctions lowers the upset rate without requiring performance tradeoff. Three mechanisms for reducing the fraction...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 1987-12, Vol.34 (6), p.1796-1799
Main Authors: McNulty, P. J., Lynch, J. E., Abdel-Kader, W. G.
Format: Article
Language:English
Subjects:
Charge measurement
Current measurement
Electric variables measurement
FETs
Particle measurements
Protons
Reflection
Solid modeling
Space charge
Substrates
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Single event upsets in microelectronic circuits follow the collection of more than some critical amount of charge at certain reverse-biased junctions. Reducing charge collection at the junctions lowers the upset rate without requiring performance tradeoff. Three mechanisms for reducing the fraction of charge collected at a junction can be incorporated in the use of CMOS-type wells. For illustration the CHMOS-III-D process used in Intel's P51C256 is shown to lower the error rate to be expected in deep space by an order of magnitude from that calculated for an equivalent dRAM of standard design.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.1987.4337557