MOSFET optimization in deep submicron technology for charge amplifiers

The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the enhanced MOSFET model,...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2005-12, Vol.52 (6), p.3223-3232
Main Authors: De Geronimo, G., O'Connor, P.
Format: Article
Language:English
Subjects:
Amplifiers
Capacitance
Channels
Charge
Charge amplifier
Circuit noise
CMOS
CMOS technology
Design optimization
Equivalence
Filters
Low-frequency noise
MOSFET
MOSFET circuits
MOSFETs
Noise
Optimization
Semiconductor device modeling
Sensor phenomena and characterization
Signal resolution
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the enhanced MOSFET model, when compared to the classical, produces a different resolution estimate and input MOSFET optimization result. The minimum channel length and the maximum allocated power are not always the best choice in terms of resolution. Also, in an optimized front-end, the low frequency noise contribution to the Equivalent Noise Charge may depend on the time constant of the filter. As an example, results from the commercial TSMC 0.25 mum CMOS technology are reported
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2005.862938