Design and test issues of an FPGA based data acquisition system for medical imaging using PEM

The main aspects of the design and test (D&T) of a reconfigurable architecture for the Data Acquisition Electronics (DAE) system of the Clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (Positron Emission Mammography) detector with 12288...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2006-06, Vol.53 (3), p.761-769
Main Authors: Leong, C., Bento, P., Lousa, P., Joao Nobre, Rego, J., Rodrigues, P., Silva, J.C., Teixeira, I.C., Teixeira, J.P., Trindade, A., Varela, J.
Format: Article
Language:English
Subjects:
Automatic testing
Biomedical imaging
Built-in self-test
Channels
Data acquisition
Design engineering
Detectors
Electronic equipment testing
Electronics
Field programmable gate arrays
Functional built-in self test
hierarchy
Life testing
Logic
Medical imaging
Medical tests
modularity
parallelism
parameterization
Parametrization
pipelining
process diagrams
re-use
System testing
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Summary:The main aspects of the design and test (D&T) of a reconfigurable architecture for the Data Acquisition Electronics (DAE) system of the Clear-PEM detector are presented in this paper. The application focuses medical imaging using a compact PEM (Positron Emission Mammography) detector with 12288 channels, targeting high sensitivity and spatial resolution. The DAE system processes data frames that come from a front-end (FE) electronics, identifies the relevant data and transfers it to a PC for image processing. The design is supported in a novel D&T methodology, in which hierarchy, modularity and parallelism are extensively exploited to improve design and testability features. Parameterization has also been used to improve design flexibility. Nominal frequency is 100 MHz. The DAE must respond to a data acquisition rate of 1 million relevant events (coincidences) per second, under a total single photon background rate in the detector of 10 MHz. Trigger and data acquisition logic is implemented in eight 4-million, one 2-million and one 1-million gate FPGAs (Xilinx Virtex II). Functional Built-In Self Test (BIST) and Debug features are incorporated in the design to allow on-board FPGA testing and self-testing during product lifetime.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2006.874841