An SEU/SET-Tolerant Phase Frequency Detector With Double-Loop Self-Sampling Technology for Clock Data Recovery

A hardened phase frequency detector (PFD) employing double-loop self-sampling technology is proposed for clock and data recovery. The PFD can remove the error state and maintain the correct state by the use of the sampler. The laser experiment shows that the threshold value of the proposed PFD has b...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on nuclear science 2019-07, Vol.66 (7), p.1483-1490
Main Authors: Hengzhou, Yuan, Jianjun, Chen, Bin, Liang, Yaqing, Chi, Xi, Chen, Yang, Guo
Format: Article
Language:English
Subjects:
Bit error rate
Charge pumps
Clock data recovery
Clocks
Data recovery
Error correction
Phase frequency detector
phase frequency detector (PFD)
radiation hardening
Sampling
Single event upsets
Technology
Transistors
Voltage-controlled oscillators
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A hardened phase frequency detector (PFD) employing double-loop self-sampling technology is proposed for clock and data recovery. The PFD can remove the error state and maintain the correct state by the use of the sampler. The laser experiment shows that the threshold value of the proposed PFD has been greatly improved.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2019.2922673