Generation of High-Resolution 12-Sided Voltage Space Vector Structure Using Low-Voltage Stacked and Cascaded Basic Inverter Cells

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-le...

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Bibliographic Details
Published in:IEEE transactions on power electronics 2018-09, Vol.33 (9), p.7349-7358
Main Authors: Yadav, Apurv Kumar, Boby, Mathews, Pramanick, Sumit Kumar, Gopakumar, K., Umanand, Loganathan, Franquelo, Leopoldo G.
Format: Article
Language:English
Subjects:
Batteries
Capacitors
Cascaded H-bridge (CHB)
dodecagonal space vector structure (DVSVS)
Flight
Harmonic analysis
induction motor drive (IMD)
Induction motors
Inverters
Low voltage
multilevel converter
Power factor
Square waves
stacked inverter
Stacking
Switches
Switching
Switching loss
Topology
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Summary:This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme.
ISSN:0885-8993
1941-0107
DOI:10.1109/TPEL.2017.2764541