Design and Implementation of Two Hybrid High Frequency DPWMs Using Delay Blocks on FPGAs

• Published in: IEEE transactions on power electronics 2021-12, Vol.36 (12), p.14567-14578
• Main Authors: Fernandez-Gomez, Marcos, Sanchez, Alberto, de Castro, Angel, Lopez, Jaime, Zumel, Pablo, Fernandez, Cristina
• Format: Article
• Language: English
• Subjects: Clocks; Comparators; Complementary signal; Converters; dc–dc converters; dead time; Delay lines; Delays; Dynamic tests; Field programmable gate arrays; field programmable gate arrays (FPGA); High frequencies; High resolution; hybrid DPWM; low-cost FPGA; Modulators; Pulse duration; Pulse width modulation; Signal resolution; Tuning
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2021.3091306

The use of very high-resolution digital pulse width modulators (DPWMs) for high frequency dc-dc converters has been steadily increasing in recent years. However, the resolution of the DPWM formed by counters and comparators is limited when the switching frequency rise above MHz range. Given this limitation, new strategies for DPWM architectures are being designed to increase the resolution of the signals. This article proposes two new DPWMs architectures with the aim of increasing the resolution of trigger signals using field programmable gate arrays (FPGAs). The first proposed architecture is a hybrid DPWM, which integrates a clock manager and a delay line. For this architecture, the delay line is configured using FPGA intellectual properties (IP) blocks. This delay stage allows a fine resolution in the picosecond scale. In addition, an alternative solution has been implemented to generate two signals, the main signal and its complementary one, including high resolution for the dead time, which is also configurable. Both architectures have been tested through static and dynamic tests on two FPGAs of different costs, an Artix-7 (low-cost) and a Kintex-UltraScale 7 (high-cost) by Xilinx.