A Formal Verification Method for the SOPC Software

System on programmable chip (SOPC) is a kind of system on a programmable chip. The system architecture is superior to the traditional design pattern. The system has an on -chip bus between the processor and the programmable logic, which forms a high bandwidth, low latency, connection, and has rich f...

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Bibliographic Details
Published in:IEEE transactions on reliability 2022-06, Vol.71 (2), p.818-829
Main Authors: Zhou, Shan, Wang, Jinbo, Jia, Jiao, Zhang, Chi, Wang, Ruixue
Format: Article
Language:English
Subjects:
Algorithms
Architecture verification
Computer architecture
Data buses
Dynamic tests
Errors
formal verification
Hardware
IP networks
Microprocessors
Modelling
Network latency
Physical tests
Power consumption
Reliability
Security
Software
SOPC
System-on-chip
Test methods
Testing
various forms IP abstraction
Verification
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Summary:System on programmable chip (SOPC) is a kind of system on a programmable chip. The system architecture is superior to the traditional design pattern. The system has an on -chip bus between the processor and the programmable logic, which forms a high bandwidth, low latency, connection, and has rich flexible customization of IP. It also has advantages of low power consumption and high performance. The application in the field of high reliable proportion rising year by year. However, the change of system architecture and the expansion of software scale have brought great impact on the simulation test method and the physical test method. The existing dynamic testing methods are based on limited testing scenarios to investigate the system. It is difficult to find hidden errors in the design of complex connection segments, such as the errors in the on -chip bus transmission, the errors in the hardware and software coupling, and so on. Due to system scale of the state-space explosion problem and various forms IP, SOPC cannot apply formal verification techniques. In this article, we propose a SOPC formalized validation framework. It is based on polymorphous IP abstraction modeling, common formal properties analysis, and modeling methods in system architecture and other high-risk areas. The experimental results show that the proposed algorithm and the established SOPC formal verification framework can introduce the formal verification technique to SOPC high-risk area verification, and it can be used as the guidance of SOPC formal verification.
ISSN:0018-9529
1558-1721
DOI:10.1109/TR.2022.3166548