Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

• Published in: IEEE transactions on semiconductor manufacturing 2008-02, Vol.21 (1), p.110-115
• Main Authors: Yasuda, Y., Yamamoto, I., Yamagata, Y., Imai, K.
• Format: Article
• Language: English
• Subjects: Amorphous-Si (a-Si); Applied sciences; Degradation; Devices; Dielectric materials; Dielectrics; Electrodes; Electronics; Exact sciences and technology; Gate leakage; gate-induced drain leakage (GIDL); Gates; HfSiON; High K dielectric materials; high-k; High-K gate dielectrics; Insertion; Leakage; Manufacturing processes; National electric code; phosphorus; positive bias temperature instability (PBTI); reliability; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Silicon oxynitride; Temperature; Transistors
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2007.914382

We have proposed a novel poly-Si/a-Si/HfSiON transistor to enhance reliabilities without performance degradation for a 65-nm-node low standby power (LSTP) application. By insertion of a thin amorphous-Si layer between the Poly-Si gate electrode and HfSiON, both phosphorus penetration from gate electrode and a reaction at gate electrode/HfSiON interface are successfully suppressed, so that positive bias temperature instability, one of the biggest issues for high-k gate dielectric, is drastically improved by two orders of magnitude. By carefully optimizing the gate stack structure of HfSiON, the HfSiON device can satisfy both lower gate leakage and gate-induced drain leakage at the same time. As a result, an excellent I on - I standby (= I g + l off ) characteristic can be achieved, compared to the conventional SiON device. The a-Si insertion technique can realize the combination between the high-k gate dielectric and Poly-Si for future LSTP applications.