A Regularized Singular Value Decomposition-Based Approach for Failure Pattern Classification on Fail Bit Map in a DRAM Wafer

• Published in: IEEE transactions on semiconductor manufacturing 2015-02, Vol.28 (1), p.41-49
• Main Authors: Byunghoon Kim, Young-Seon Jeong, Seung Hoon Tong, In-Kap Chang, Myong-Kee Jeongyoung
• Format: Article
• Language: English
• Subjects: Accuracy; Artificial neural networks; Dynamic random access memory (DRAM); fail bit maps (FBMs); Feature extraction; Matrix decomposition; Pattern classification; Random access memory; Singular value decomposition; wafer quality
• ISSN: 0894-6507; 1558-2345
• DOI: 10.1109/TSM.2014.2388192

In semiconductor manufacturing processes, monitoring the quality of wafers is one of the most important steps to quickly detect process faults and significantly reduce yield loss. Fail bit maps (FBMs) represent the failed cell count during wafer functional tests and have been popularly used as one of the diagnosis tools in semiconductor manufacturing for process monitoring, root cause analysis, and yield improvements. However, the visual inspection process is costly and time-consuming. Therefore, this paper proposes an automated classification procedure for failure patterns on FBMs in dynamic random access memory (DRAM) wafers. The novel matrix factorization approach, called regularized singular value decomposition, is proposed to decompose binarized FBMs into several eigen-images to extract features that can provide the characteristics of the failure patterns on FBMs. By using the extracted features, k-nearest neighbor classifier is employed to classify feature patterns on FBMs into single bit failure maps and non-single bit failure ones. The proposed procedure is tested on real-life DRAM wafer data set provided by a semiconductor manufacturing industry, and promising results have been obtained for the automatic classification of single bit and non-single bit failure maps.