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Multi-Gb/s Software Decoding of Polar Codes
This paper presents an optimized software implementation of a Successive Cancellation (SC) decoder for polar codes. Despite the strong data dependencies in SC decoding, a highly parallel software polar decoder is devised for x86 processor target. A high level of performance is achieved by exploiting...
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Published in: | IEEE transactions on signal processing 2015-01, Vol.63 (2), p.349-359 |
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creator | Le Gal, Bertrand Leroux, Camille Jego, Christophe |
description | This paper presents an optimized software implementation of a Successive Cancellation (SC) decoder for polar codes. Despite the strong data dependencies in SC decoding, a highly parallel software polar decoder is devised for x86 processor target. A high level of performance is achieved by exploiting the parallelism inherent in today's processor architectures (SIMD, multicore, etc.). Some optimizations that were originally thought for hardware implementation (memory reduction techniques and algorithmic simplifications) were also applied to enhance the throughput of the software implementation. Finally, some low level optimizations such as explicit assembly description or data packing are used to improve the throughput even more. The resulting decoder description is implemented on different x86 processor targets. An analysis of the decoder in terms of latency and throughput is proposed. The influence of several parameters on the throughput and the latency is investigated: the selected target, the code rate, the code length, the SIMD mode (SSE/AVX), the multithreading mode, etc. The energy per decoded bit is also estimated. The proposed software decoder compares favorably with state of the art software polar decoders. Extensive experimentations demonstrate that the proposed software polar decoder exceeds 1 Gb/s for code lengths N ≤ 2 17 on a single core and reaches multi-Gb/s throughputs when using four cores in parallel in AVX mode. |
doi_str_mv | 10.1109/TSP.2014.2371781 |
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Despite the strong data dependencies in SC decoding, a highly parallel software polar decoder is devised for x86 processor target. A high level of performance is achieved by exploiting the parallelism inherent in today's processor architectures (SIMD, multicore, etc.). Some optimizations that were originally thought for hardware implementation (memory reduction techniques and algorithmic simplifications) were also applied to enhance the throughput of the software implementation. Finally, some low level optimizations such as explicit assembly description or data packing are used to improve the throughput even more. The resulting decoder description is implemented on different x86 processor targets. An analysis of the decoder in terms of latency and throughput is proposed. The influence of several parameters on the throughput and the latency is investigated: the selected target, the code rate, the code length, the SIMD mode (SSE/AVX), the multithreading mode, etc. The energy per decoded bit is also estimated. The proposed software decoder compares favorably with state of the art software polar decoders. Extensive experimentations demonstrate that the proposed software polar decoder exceeds 1 Gb/s for code lengths N ≤ 2 17 on a single core and reaches multi-Gb/s throughputs when using four cores in parallel in AVX mode.</description><identifier>ISSN: 1053-587X</identifier><identifier>EISSN: 1941-0476</identifier><identifier>DOI: 10.1109/TSP.2014.2371781</identifier><identifier>CODEN: ITPRED</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Computer programs ; Decoders ; Decoding ; Microprocessors ; Optimization ; Polar codes ; Reduction ; Signal processing algorithms ; SIMD ; Software ; software optimizations ; successive cancellation decoding ; Systematics ; Throughput ; Vectors ; x86 processor</subject><ispartof>IEEE transactions on signal processing, 2015-01, Vol.63 (2), p.349-359</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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Despite the strong data dependencies in SC decoding, a highly parallel software polar decoder is devised for x86 processor target. A high level of performance is achieved by exploiting the parallelism inherent in today's processor architectures (SIMD, multicore, etc.). Some optimizations that were originally thought for hardware implementation (memory reduction techniques and algorithmic simplifications) were also applied to enhance the throughput of the software implementation. Finally, some low level optimizations such as explicit assembly description or data packing are used to improve the throughput even more. The resulting decoder description is implemented on different x86 processor targets. An analysis of the decoder in terms of latency and throughput is proposed. The influence of several parameters on the throughput and the latency is investigated: the selected target, the code rate, the code length, the SIMD mode (SSE/AVX), the multithreading mode, etc. The energy per decoded bit is also estimated. The proposed software decoder compares favorably with state of the art software polar decoders. Extensive experimentations demonstrate that the proposed software polar decoder exceeds 1 Gb/s for code lengths N ≤ 2 17 on a single core and reaches multi-Gb/s throughputs when using four cores in parallel in AVX mode.</description><subject>Algorithms</subject><subject>Computer programs</subject><subject>Decoders</subject><subject>Decoding</subject><subject>Microprocessors</subject><subject>Optimization</subject><subject>Polar codes</subject><subject>Reduction</subject><subject>Signal processing algorithms</subject><subject>SIMD</subject><subject>Software</subject><subject>software optimizations</subject><subject>successive cancellation decoding</subject><subject>Systematics</subject><subject>Throughput</subject><subject>Vectors</subject><subject>x86 processor</subject><issn>1053-587X</issn><issn>1941-0476</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><recordid>eNpdkE1LAzEQhoMoWKt3wcuCF0G2zeRjkxyl1SpULLSCt5DdTWTLtqnJLuK_N6XFg6cZmOedGR6ErgGPALAar5aLEcHARoQKEBJO0AAUgxwzUZymHnOacyk-ztFFjGucSKaKAbp_7duuyWflOGZL77pvE2w2tZWvm-1n5l228K0J2cTXNl6iM2faaK-OdYjenx5Xk-d8_jZ7mTzM84oS1uW8MLwuqUyHMbOqUk4oApSUNcXCcUuFASLBSIadNU7gqpQ1EJ6GUhIo6RDdHfbugv_qbez0pomVbVuztb6PGgoOVBVEsYTe_kPXvg_b9F2ilCKMg-KJwgeqCj7GYJ3ehWZjwo8GrPf2dLKn9_b00V6K3BwijbX2Dy9UgbGQ9Bf5y2ei</recordid><startdate>20150115</startdate><enddate>20150115</enddate><creator>Le Gal, Bertrand</creator><creator>Leroux, Camille</creator><creator>Jego, Christophe</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>F28</scope><scope>FR3</scope><orcidid>https://orcid.org/0000-0003-2269-8756</orcidid></search><sort><creationdate>20150115</creationdate><title>Multi-Gb/s Software Decoding of Polar Codes</title><author>Le Gal, Bertrand ; Leroux, Camille ; Jego, Christophe</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c324t-56a5db3847604e9c9f792132bd307f5e37a1281a840feaf70cb8d12507f8821b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2015</creationdate><topic>Algorithms</topic><topic>Computer programs</topic><topic>Decoders</topic><topic>Decoding</topic><topic>Microprocessors</topic><topic>Optimization</topic><topic>Polar codes</topic><topic>Reduction</topic><topic>Signal processing algorithms</topic><topic>SIMD</topic><topic>Software</topic><topic>software optimizations</topic><topic>successive cancellation decoding</topic><topic>Systematics</topic><topic>Throughput</topic><topic>Vectors</topic><topic>x86 processor</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Le Gal, Bertrand</creatorcontrib><creatorcontrib>Leroux, Camille</creatorcontrib><creatorcontrib>Jego, Christophe</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on signal processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Le Gal, Bertrand</au><au>Leroux, Camille</au><au>Jego, Christophe</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Multi-Gb/s Software Decoding of Polar Codes</atitle><jtitle>IEEE transactions on signal processing</jtitle><stitle>TSP</stitle><date>2015-01-15</date><risdate>2015</risdate><volume>63</volume><issue>2</issue><spage>349</spage><epage>359</epage><pages>349-359</pages><issn>1053-587X</issn><eissn>1941-0476</eissn><coden>ITPRED</coden><abstract>This paper presents an optimized software implementation of a Successive Cancellation (SC) decoder for polar codes. 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The influence of several parameters on the throughput and the latency is investigated: the selected target, the code rate, the code length, the SIMD mode (SSE/AVX), the multithreading mode, etc. The energy per decoded bit is also estimated. The proposed software decoder compares favorably with state of the art software polar decoders. Extensive experimentations demonstrate that the proposed software polar decoder exceeds 1 Gb/s for code lengths N ≤ 2 17 on a single core and reaches multi-Gb/s throughputs when using four cores in parallel in AVX mode.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TSP.2014.2371781</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0003-2269-8756</orcidid></addata></record> |
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subjects | Algorithms Computer programs Decoders Decoding Microprocessors Optimization Polar codes Reduction Signal processing algorithms SIMD Software software optimizations successive cancellation decoding Systematics Throughput Vectors x86 processor |
title | Multi-Gb/s Software Decoding of Polar Codes |
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