The Impact of CPU Voltage Margins on Power-Constrained Execution

CPUs typically operate at a voltage which is higher than what is strictly required, using voltage margins to account for process variability and anticipate any combination of adverse operating conditions. However, these worst-case scenarios occur rarely, if ever, thus the operating voltage is overly...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on sustainable computing 2022-01, Vol.7 (1), p.221-234
Main Authors: Koutsovasilis, Panos, Antonopoulos, Christos D., Bellas, Nikolaos, Lalis, Spyros, Papadimitriou, George, Chatzidimitriou, Athanasios, Gizopoulos, Dimitris
Format: Article
Language:English
Subjects:
Capping
Central processing units
Checkpointing
Clocks
CPU power capping
CPU voltage margins reduction
CPUs
Electric potential
Hardware
performance of systems
Power demand
power management
Power system management
Program processors
Software
Voltage
Voltage control
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:CPUs typically operate at a voltage which is higher than what is strictly required, using voltage margins to account for process variability and anticipate any combination of adverse operating conditions. However, these worst-case scenarios occur rarely, if ever, thus the operating voltage is overly pessimistic resulting in excessive power dissipation which leads to decreased performance under power capping. In this paper, we investigate the impact of reducing voltage margins beyond the nominal level on the efficiency of CPU power capping mechanisms, for three commercial systems, two Applied Micro ARMv8 micro-servers (X-Gene2 and X-Gene3) and an Intel x86-64 (Xeon E3). We show that CPU power capping at reduced voltage margins compared with Intel's RAPL and Dynamic Frequency Scaling (DFS) mechanisms results in performance improvement by up to 64 and 24 percent on average, respectively. In combination with state-of-the-art thread packing, the reduction of CPU voltage margins results in 36, 33 and 27 percent performance improvement compared with RAPL and DFS for the Xeon E3 and the X-Gene processors, respectively. Also, we validate the robustness of our approach with a set of long-running experiments and show that significant energy gains can be achieved even when considering the cost of checkpointing and recovery in large-scale systems.
ISSN:2377-3782
2377-3790
DOI:10.1109/TSUSC.2020.3045195