Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays

• Published in: IEEE transactions on ultrasonics, ferroelectrics, and frequency control ferroelectrics, and frequency control, 2005-12, Vol.52 (12), p.2235-2241
• Main Authors: Cicek, I., Bozkurt, A., Karaman, M.
• Format: Article
• Language: English
• Subjects: Acoustic arrays; Acoustic imaging; Acoustic signal processing; Acoustics; Arrays; Circuit design; Circuit testing; Circuits; CMOS technology; Computer Simulation; Computer-Aided Design; Design; Design engineering; Electric Capacitance; Electronics, Medical; Equipment Design - methods; Equipment Failure Analysis; Exact sciences and technology; Finite Element Analysis; Fundamental areas of phenomenology (including applications); General equipment and techniques; Image Enhancement - instrumentation; Image Enhancement - methods; Imaging, Three-Dimensional - instrumentation; Imaging, Three-Dimensional - methods; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Integrated circuits; Linear Models; Mathematical models; Membranes, Artificial; Microelectrodes; Miniaturization; Performance analysis; Physics; Pulse amplifiers; Pulse circuits; Semiconductors; Systems Integration; Three dimensional; Transducers; Transduction; acoustical devices for the generation and reproduction of sound; Two dimensional; Ultrasonic imaging; Ultrasonic transducer arrays; Ultrasonic transducers; Ultrasonics, quantum acoustics, and physical effects of sound; Ultrasonography - instrumentation; Ultrasonography - methods
• ISSN: 0885-3010; 1525-8955
• DOI: 10.1109/TUFFC.2005.1563266

Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 /spl times/ 4 array of the designed circuit cells, each cell occupying a 200 /spl times/ 200 /spl mu/m/sup 2/ area, was formed for the initial test studies and scheduled for fabrication in 0.8 /spl mu/m, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.