Testable Designs of Multiple Precharged Domino Circuits

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2007-04, Vol.15 (4), p.461-465
• Main Authors: Haniotakis, T., Tsiatouhas, Y., Nikolos, D., Efstathiou, C.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit faults; Circuit noise; Circuit properties; Circuit testing; Circuits; CMOS logic circuits; Design engineering; Design for testability; Design. Technologies. Operation analysis. Testing; Digital circuits; Domino CMOS; Electric, optical and optoelectronic circuits; Electrical fault detection; Electronic circuits; Electronics; Exact sciences and technology; Fault detection; Faults; Informatics; Integrated circuits; Logic testing; multiple precharge; Noise; Noise reduction; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testability; Testing, measurement, noise and reliability; Transistors; Very large scale integration; Working environment noise
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2007.893664

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults