Constrained Asynchronous Ring Structures for Robust Digital Oscillators

On-chip digital oscillators are ubiquitous in every communication applications like in RF architectures or intra-chip communication systems. Actually, their integration to the standard CMOS design flow, their ability to generate high-frequency signals, as well as their configurability make them real...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2009-07, Vol.17 (7), p.907-919
Main Authors: Hamon, J., Fesquet, L., Miscopein, B., Renaudin, M.
Format: Article
Language:English
Subjects:
3-D Charlie model
Bursting
Design
Design engineering
Digital
Digital oscillators
Engineering Sciences
Micro and nanotechnologies
Microelectronics
Oscillating
Oscillators
process variability
Radio frequency
Ring oscillators
Ring structures
Robustness
self-timed rings
Signal design
Signal generators
Stability
System-on-a-chip
Temperature sensors
Time measurements
Timing
Very large scale integration
Voltage-controlled oscillators
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Summary:On-chip digital oscillators are ubiquitous in every communication applications like in RF architectures or intra-chip communication systems. Actually, their integration to the standard CMOS design flow, their ability to generate high-frequency signals, as well as their configurability make them really attractive for designers. However, these kinds of digital oscillators suffer from their sensitivity to any process, voltage, or temperature variations. Self-timed systems are usually considered robust to these kinds of variations. This paper proposes the use of self-timed ring structures for generating high-resolution timing signals. One of the main difficulties when designing such oscillators is to avoid burst oscillating modes and produce uniformly spaced events in order to act as a periodic time-base. Based on a high-level ring model, enriched with stage switching timing information, the temporal behavior of oscillating self-timed rings is studied and their robustness to process variability is evaluated. Several ring architectures are explored to take advantage of complex combination of stages I/Os and it is shown that one can tune a tradeoff between oscillation period and signal stability. In addition, the paper provides designers with the ability to easily prevent burst oscillating modes by applying a very tractable ring design rule. Electrical simulations demonstrate the correctness and efficiency of the approach.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2008.2011801