Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2010-09, Vol.18 (9), p.1337-1347
• Main Authors: Mitev, A, Marefat, M, Dongsheng Ma, Wang, J M
• Format: Article
• Language: English
• Subjects: Benchmarks; Circuit analysis; Circuit optimization; Circuit testing; Circuits; CMOS; CMOS process; CMOS technology; Delay; Errors; Integrated circuit interconnections; Mathematical models; Networks; Performance analysis; Principle Hessian directions (PHDs); process variation; Random variables; Reduction; Semiconductor device modeling; Studies; timing analysis; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2009.2024340

As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. To accurately consider both global and local process variations, a large number of random variables (or parameters) have to be incorporated into circuit models. This in turn raises the complexity of the circuit models. In this paper, we propose a principle Hessian direction-based parameter-reduction approach. This new approach relies on the impact of each parameter on circuit performance to decide whether keeping or reducing the parameter. Compared with the existing principle component analysis method, this performance based property provides us a significantly smaller set of parameters after reduction. The experimental results also support our conclusions. In interconnect cases, the proposed method reduces 70% of parameters. In some cases, for example, the mesh circuit in the current paper, the new approach leads to an 85% reduction. We also tested ISCAS benchmarks. In all cases, an average of 53% of reduction is observed with less than 3% error in the mean value and less than 8% error in the variation.