CMOS Full-Adders for Energy-Efficient Arithmetic Applications

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2011-04, Vol.19 (4), p.718-721
Main Authors: Aguirre-Hernandez, Mariano, Linares-Aranda, Monico
Format: Article
Language:English
Subjects:
Applied sciences
Arithmetic
Circuit properties
CMOS
CMOS logic circuits
CMOS technology
Delay
Design. Technologies. Operation analysis. Testing
Digital circuits
Digital signal processing
Display
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy consumption
Energy efficiency
Exact sciences and technology
Frequency
full-adder
High speed
Integrated circuits
Logic
Logic design
low-power
Power consumption
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Simulation
Testing
Transistors
Very large scale integration
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Summary:We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-μm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2009.2038166