Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits

Ground distribution network noise produced during sleep-to-active mode transitions is an important reliability concern in standard multi-threshold CMOS (MTCMOS) circuits. Different noise-aware sequential MTCMOS circuits are explored in this paper. A low-leakage data retention sleep mode is implement...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2011-05, Vol.19 (5), p.763-773
Main Authors: Hailong Jiao, Kursun, V
Format: Article
Language:English
Subjects:
Applied sciences
Circuit noise
Circuit properties
Circuit stability
CMOS technology
Data retention
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy consumption
Exact sciences and technology
Flip-flops
flip-flops (FFs)
Integrated circuit noise
Integrated circuits
latches
low leakage sleep mode
multi-threshold CMOS (MTCMOS)
Noise level
Noise reduction
on-chip noise
power and ground distribution networks
power gating
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sequential circuits
Space technology
Transistors
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Summary:Ground distribution network noise produced during sleep-to-active mode transitions is an important reliability concern in standard multi-threshold CMOS (MTCMOS) circuits. Different noise-aware sequential MTCMOS circuits are explored in this paper. A low-leakage data retention sleep mode is implemented with smaller centralized sleep transistors to suppress the ground bouncing noise produced during reactivation events in sequential MTCMOS circuits. Ground bouncing noise, leakage power consumption, data stability, and area overheads of different sequential MTCMOS circuits are evaluated with a 90-nm CMOS technology. The peak amplitude of ground bouncing noise is reduced by up to 94.16% with the noise-aware MTCMOS techniques as compared to the conventional Mutoh flip-flop. The application space of different data retention MTCMOS circuit techniques is identified with various design metrics in this paper.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2009.2039761