Testing Methodology of Embedded DRAMs

The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the le...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2012-09, Vol.20 (9), p.1715-1728
Main Authors: Hao-Yu Yang, Chi-Min Chang, Chao, M. C., Rei-Fu Huang, Shih-Chin Lin
Format: Article
Language:English
Subjects:
Algorithm design and analysis
Algorithms
Applied sciences
Architecture
Circuit properties
Commodities
Defects
Design. Technologies. Operation analysis. Testing
Dynamic random access memory
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Embedded-DRAM (eDRAM)
Error correction codes
error-correction-code
Exact sciences and technology
fault model
Integrated circuits
Integrated circuits by function (including memories and processors)
Mathematical model
Mathematical models
Random access memory
retention
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Static random access memory
Switching, multiplexing, switched capacity circuits
Testing
Transistors
Very large scale integration
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Summary:The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2011.2161785