Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor

This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of s...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2013-02, Vol.21 (2), p.193-205
Main Authors: Rossi, D., Mucci, C., Campi, F., Spolzino, S., Vanzolini, L., Sahlbach, H., Whitty, S., Ernst, R., Putzke-Roming, W., Guerrieri, R.
Format: Article
Language:English
Subjects:
Advanced Encryption Standard (AES)
application-specific signal processors (ASSP)
Applied sciences
Arrays
binarization CGRA
Circuit properties
Cyclic redundancy check (CRC)
Design. Technologies. Operation analysis. Testing
Digital circuits
digital signal processor (DSP)
Digital signal processors
dynamic frequency scaling
edge detection
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
energy efficiency
Engines
ethernet
Exact sciences and technology
field-programmable gate array (FPGA)
Integrated circuits
Integrated circuits by function (including memories and processors)
Kernel
motion compensation (MC)
motion estimation (ME)
Performance evaluation
reconfigurable computing
RGB2YUV
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal processing
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Summary:This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2012.2185963