Loading…

Cell-Based Process Resilient Multiphase Clock Generation

Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (de...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2013-12, Vol.21 (12), p.2348-2352
Main Authors: Ding, Ruo-Ting, Huang, Shi-Yu, Tzeng, Chao-Wen
Format: Article
Language:English
Subjects:
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c328t-62652e5ef84e6e6422b205717797bdbaa2e22265ea90b485dae6c5fe2a5d9d983
cites cdi_FETCH-LOGICAL-c328t-62652e5ef84e6e6422b205717797bdbaa2e22265ea90b485dae6c5fe2a5d9d983
container_end_page 2352
container_issue 12
container_start_page 2348
container_title IEEE transactions on very large scale integration (VLSI) systems
container_volume 21
creator Ding, Ruo-Ting
Huang, Shi-Yu
Tzeng, Chao-Wen
description Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness.
doi_str_mv 10.1109/TVLSI.2012.2230347
format article
fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TVLSI_2012_2230347</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6392302</ieee_id><sourcerecordid>1464568038</sourcerecordid><originalsourceid>FETCH-LOGICAL-c328t-62652e5ef84e6e6422b205717797bdbaa2e22265ea90b485dae6c5fe2a5d9d983</originalsourceid><addsrcrecordid>eNpdkM1OwzAQhC0EEqXwAnCJxIVLir3-iX2ECkqlIhAUrpaTbERKmhQ7OfD2uLTiwF52pflmNRpCzhmdMEbN9fJ98TqfAGUwAeCUi-yAjJiUWWriHMabKp5qYPSYnISwopQJYeiI6Ck2TXrrApbJs-8KDCF5wVA3NbZ98jg0fb35iGoybbriM5lhi971ddeekqPKNQHP9ntM3u7vltOHdPE0m09vFmnBQfepAiUBJVZaoEIlAHKgMmNZZrK8zJ0DBIgMOkNzoWXpUBWyQnCyNKXRfEyudn83vvsaMPR2XYcihnYtdkOwTCghlaZ8i17-Q1fd4NuYLlICDAelZaRgRxW-C8FjZTe-Xjv_bRm12zLtb5l2W6bdlxlNFztTjYh_BsVN1IH_AFKcbsU</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1442932685</pqid></control><display><type>article</type><title>Cell-Based Process Resilient Multiphase Clock Generation</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Ding, Ruo-Ting ; Huang, Shi-Yu ; Tzeng, Chao-Wen</creator><creatorcontrib>Ding, Ruo-Ting ; Huang, Shi-Yu ; Tzeng, Chao-Wen</creatorcontrib><description>Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2012.2230347</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Buffers ; Calibration ; Clock generation ; Clocks ; cyclic property ; Delay ; Design engineering ; Multiphase ; multiphase clock ; Phases ; process resilient ; Tuning ; Very large scale integration</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2348-2352</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Dec 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c328t-62652e5ef84e6e6422b205717797bdbaa2e22265ea90b485dae6c5fe2a5d9d983</citedby><cites>FETCH-LOGICAL-c328t-62652e5ef84e6e6422b205717797bdbaa2e22265ea90b485dae6c5fe2a5d9d983</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6392302$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,27901,27902,54771</link.rule.ids></links><search><creatorcontrib>Ding, Ruo-Ting</creatorcontrib><creatorcontrib>Huang, Shi-Yu</creatorcontrib><creatorcontrib>Tzeng, Chao-Wen</creatorcontrib><title>Cell-Based Process Resilient Multiphase Clock Generation</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness.</description><subject>Buffers</subject><subject>Calibration</subject><subject>Clock generation</subject><subject>Clocks</subject><subject>cyclic property</subject><subject>Delay</subject><subject>Design engineering</subject><subject>Multiphase</subject><subject>multiphase clock</subject><subject>Phases</subject><subject>process resilient</subject><subject>Tuning</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><recordid>eNpdkM1OwzAQhC0EEqXwAnCJxIVLir3-iX2ECkqlIhAUrpaTbERKmhQ7OfD2uLTiwF52pflmNRpCzhmdMEbN9fJ98TqfAGUwAeCUi-yAjJiUWWriHMabKp5qYPSYnISwopQJYeiI6Ck2TXrrApbJs-8KDCF5wVA3NbZ98jg0fb35iGoybbriM5lhi971ddeekqPKNQHP9ntM3u7vltOHdPE0m09vFmnBQfepAiUBJVZaoEIlAHKgMmNZZrK8zJ0DBIgMOkNzoWXpUBWyQnCyNKXRfEyudn83vvsaMPR2XYcihnYtdkOwTCghlaZ8i17-Q1fd4NuYLlICDAelZaRgRxW-C8FjZTe-Xjv_bRm12zLtb5l2W6bdlxlNFztTjYh_BsVN1IH_AFKcbsU</recordid><startdate>20131201</startdate><enddate>20131201</enddate><creator>Ding, Ruo-Ting</creator><creator>Huang, Shi-Yu</creator><creator>Tzeng, Chao-Wen</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20131201</creationdate><title>Cell-Based Process Resilient Multiphase Clock Generation</title><author>Ding, Ruo-Ting ; Huang, Shi-Yu ; Tzeng, Chao-Wen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c328t-62652e5ef84e6e6422b205717797bdbaa2e22265ea90b485dae6c5fe2a5d9d983</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Buffers</topic><topic>Calibration</topic><topic>Clock generation</topic><topic>Clocks</topic><topic>cyclic property</topic><topic>Delay</topic><topic>Design engineering</topic><topic>Multiphase</topic><topic>multiphase clock</topic><topic>Phases</topic><topic>process resilient</topic><topic>Tuning</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ding, Ruo-Ting</creatorcontrib><creatorcontrib>Huang, Shi-Yu</creatorcontrib><creatorcontrib>Tzeng, Chao-Wen</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE/IET Electronic Library</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ding, Ruo-Ting</au><au>Huang, Shi-Yu</au><au>Tzeng, Chao-Wen</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Cell-Based Process Resilient Multiphase Clock Generation</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2013-12-01</date><risdate>2013</risdate><volume>21</volume><issue>12</issue><spage>2348</spage><epage>2352</epage><pages>2348-2352</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2012.2230347</doi><tpages>5</tpages></addata></record>
fulltext fulltext
identifier ISSN: 1063-8210
ispartof IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2348-2352
issn 1063-8210
1557-9999
language eng
recordid cdi_crossref_primary_10_1109_TVLSI_2012_2230347
source IEEE Electronic Library (IEL) Journals
subjects Buffers
Calibration
Clock generation
Clocks
cyclic property
Delay
Design engineering
Multiphase
multiphase clock
Phases
process resilient
Tuning
Very large scale integration
title Cell-Based Process Resilient Multiphase Clock Generation
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T09%3A50%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Cell-Based%20Process%20Resilient%20Multiphase%20Clock%20Generation&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Ding,%20Ruo-Ting&rft.date=2013-12-01&rft.volume=21&rft.issue=12&rft.spage=2348&rft.epage=2352&rft.pages=2348-2352&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2012.2230347&rft_dat=%3Cproquest_cross%3E1464568038%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c328t-62652e5ef84e6e6422b205717797bdbaa2e22265ea90b485dae6c5fe2a5d9d983%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1442932685&rft_id=info:pmid/&rft_ieee_id=6392302&rfr_iscdi=true