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Cell-Based Process Resilient Multiphase Clock Generation
Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (de...
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Published in: | IEEE transactions on very large scale integration (VLSI) systems 2013-12, Vol.21 (12), p.2348-2352 |
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creator | Ding, Ruo-Ting Huang, Shi-Yu Tzeng, Chao-Wen |
description | Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness. |
doi_str_mv | 10.1109/TVLSI.2012.2230347 |
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subjects | Buffers Calibration Clock generation Clocks cyclic property Delay Design engineering Multiphase multiphase clock Phases process resilient Tuning Very large scale integration |
title | Cell-Based Process Resilient Multiphase Clock Generation |
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