Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors

An RLC model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any poi...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2015-06, Vol.23 (6), p.993-1004
Main Author: Rius, Josep
Format: Article
Language:English
Subjects:
Capacitance
Capacitors
Impedance
Integrated circuit (IC) modeling
Integrated circuit modeling
Metals
power distribution networks (PDNs)
power supply noise (PSN)
System-on-chip
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Description
Summary:An RLC model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any point of the circuit are calculated as a function of frequency and PDN parameters. The proposed method to perform such calculation allows optimizing relevant PDN design parameters, such as number, size, and location of supply/ground pads and location of interblock decoupling capacitors, and width and pitch of metal tracks. The PDN model and impedance calculations are validated by comparing their results with SPICE simulations, giving a maximum error of less than 1%.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2014.2332189