Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches

The conventional error correcting code (ECC) schemes for caches are based on a fixed mapping between cache data words and ECC check bits, and fixed ECC word granularity. This leads to inefficient usage of the ECC check bits. We propose to manage the check bits flexibly for low-cost error protection...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2016-06, Vol.24 (6), p.2152-2164
Main Authors: Hong, Jeongkyu, Kim, Soontae
Format: Article
Language:English
Subjects:
Benchmark testing
Cache memory
Data buses
Energy consumption
Error correcting codes
Error correction codes
error protection
Errors
Integrated circuits
Management
Mapping
Performance degradation
Random access memory
Reliability
Transient analysis
transient error
Very large scale integration
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Summary:The conventional error correcting code (ECC) schemes for caches are based on a fixed mapping between cache data words and ECC check bits, and fixed ECC word granularity. This leads to inefficient usage of the ECC check bits. We propose to manage the check bits flexibly for low-cost error protection of last-level caches. The proposed ECC schemes work at the word level, whereas the conventional ECC schemes work at the cache line or set level. The proposed schemes protect only dirty words with ECC check bits using a flexible mapping. Moreover, the proposed schemes utilize variable ECC word granularities. Dirty (modified) words that are unlikely to be modified further before being evicted are collectively protected with a larger ECC word granularity. The proposed schemes reduce DRAM and data bus energy overheads by 28% and 45%, respectively, with the same area overhead as previously proposed competitive schemes. Our schemes show more energy reduction results for multicore systems without noticeable performance degradation.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2015.2506730