Optimizing the Implementation of SEC-DAEC Codes in FPGAs

Single error correction and double-adjacent error correction (SEC-DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and dec...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2016-12, Vol.24 (12), p.3538-3542
Main Authors: Sanchez-Macian, Alfonso, Reviriego, Pedro, Maestro, Juan Antonio
Format: Article
Language:English
Subjects:
Avionics
Coders
Decoders
Error correction
Error correction codes
Error correction codes (ECCs)
Field programmable gate arrays
field-programm-able gate arrays (FPGAs)
lookup tables (LUTs)
Optimization
Resource utilization
single error correction and double-adjacent error correction (SEC–DAEC)
Table lookup
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Description
Summary:Single error correction and double-adjacent error correction (SEC-DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes methods to optimize the decoder of SEC-DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2016.2556943