Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes

In this brief, a novel two-extra-column trellis min-max algorithm and the decoder architecture based on only the first minimum values are proposed for nonbinary low-density parity-check (NB-LDPC) codes. The algorithm greatly reduces the hardware complexity and improves the latency as well as the thr...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2017-05, Vol.25 (5), p.1787-1791
Main Authors: Thi, Huyen Pham, Lee, Hanho
Format: Article
Language:English
Subjects:
Algorithms
Approximation algorithms
Architecture
Binary system
Check node processing
CMOS
Codes
Complexity theory
Computer architecture
Decoding
Error correcting codes
layered decoding
Low density parity check codes
nonbinary LDPC
Reliability
Throughput
trellis min–max (TMM)
Very large scale integration
VLSI design
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Summary:In this brief, a novel two-extra-column trellis min-max algorithm and the decoder architecture based on only the first minimum values are proposed for nonbinary low-density parity-check (NB-LDPC) codes. The algorithm greatly reduces the hardware complexity and improves the latency as well as the throughput of the proposed decoder architecture compared with the previous works. A layered decoder architecture based on the proposed algorithm for (837, 726) NB-LDPC code over GF(32) is implemented with a 90-nm CMOS technology. The results show a decrease in the area of 24.6% for the check node unit and 75.6% for the whole decoder with a throughput of 1.27 Gb/s. The proposed decoder provides a lower area and a higher efficiency compared with the state of the art of high-rate NB-LDPC codes with high Galois-field order.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2017.2647985