An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications

Parallel matrix processing is a typical operation in many systems, and in particular matrix-vector multiplication (MVM) is one of the most common operations in the modern digital signal processing and digital communication systems. This paper proposes a fault-tolerant design for integer parallel MVM...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2018-01, Vol.26 (1), p.211-215
Main Authors: Zhen Gao, Qingqing Jing, Yumeng Li, Reviriego, Pedro, Maestro, Juan Antonio
Format: Article
Language:English
Subjects:
Encoding
Error correction codes
Fault tolerance
Fault tolerant systems
Field programmable gate arrays
matrix–vector multiplications (MVMs)
Parallel processing
soft errors
Very large scale integration
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Summary:Parallel matrix processing is a typical operation in many systems, and in particular matrix-vector multiplication (MVM) is one of the most common operations in the modern digital signal processing and digital communication systems. This paper proposes a fault-tolerant design for integer parallel MVMs. The scheme combines ideas from error correction codes with the self-checking capability of MVM. Field-programmable gate array evaluation shows that the proposed scheme can significantly reduce the overheads compared to the protection of each MVM on its own. Therefore, the proposed technique can be used to reduce the cost of providing fault tolerance in practical implementations.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2017.2755765