A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits. Both traditional CMOS and the state-of-art FinFET technology are taken into consideration. A circuit's lifetime distribu...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2018-11, Vol.26 (11), p.2470-2482
Main Authors: Yang, Kexin, Liu, Taizhi, Zhang, Rui, Milor, Linda
Format: Article
Language:English
Subjects:
Circuit design
CMOS
Dielectric breakdown
Digital circuit
Digital electronics
Electric breakdown
Feature extraction
FinFETs
frontend-of-line dielectric breakdown
gate-oxide breakdown (GOBD)
Layout
Layouts
lifetime simulator
Logic gates
Manufacturing cells
microprocessor
Microprocessors
middle-of-line (MOL) breakdown
Parameters
reliability
Time dependence
time-dependent dielectric breakdown (TDDB)
wearout
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Summary:This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits. Both traditional CMOS and the state-of-art FinFET technology are taken into consideration. A circuit's lifetime distribution depends on its usage and the resulting temperature profile. Emulation of the circuit operation extracts the relevant usage parameters. These parameters are converted to state probabilities at the inputs of the standard cells. The lifetime distributions of standard cells are characterized by taking into account all possible input state probabilities and die-to-die process variations. Because MOL TDDB depends on the layout, a step involved in estimating the lifetime distributions of standard cells is the analysis of the layout for MOL TDDB. Two different methods to extract the layout features are presented for traditional CMOS and FinFET technologies. By precharacterizing the standard cell lifetime distribution, our simulator can find the lifetime limiting cells in a circuit, and thus, circuit designers can replace such cells with a combination of standard cells with a longer lifetime to make the circuit more robust. The results also indicate that we need to pay more attention to the newly emerging MOL TDDB when designing new standard cells for FinFET technology.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2018.2861769