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A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator
A quadrature clock corrector uses relaxation oscillators to detect duty-cycle and quadrature phase errors by transforming them into pairs of frequencies, which are then digitized and compared. It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors....
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Published in: | IEEE transactions on very large scale integration (VLSI) systems 2019-04, Vol.27 (4), p.978-982 |
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container_title | IEEE transactions on very large scale integration (VLSI) systems |
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creator | Chae, Joo-Hyung Ko, Hyeongjun Park, Jihwan Kim, Suhwan |
description | A quadrature clock corrector uses relaxation oscillators to detect duty-cycle and quadrature phase errors by transforming them into pairs of frequencies, which are then digitized and compared. It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors. The prototype is implemented in a 55-nm CMOS process with a supply voltage of 1.2 V and occupies an area of 0.003 mm 2 . The experimental results show that the operation range is from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximum duty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phase error is 1.1° at 3 GHz. |
doi_str_mv | 10.1109/TVLSI.2018.2883730 |
format | article |
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It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors. The prototype is implemented in a 55-nm CMOS process with a supply voltage of 1.2 V and occupies an area of 0.003 mm 2 . The experimental results show that the operation range is from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximum duty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phase error is 1.1° at 3 GHz.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2018.2883730</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Capacitors ; Clocks ; CMOS ; Detectors ; Digitization ; duty cycle ; Dynamic random access memory ; Dynamic random access memory (DRAM) interface ; Frequency conversion ; Oscillators ; Phase detectors ; Phase error ; Phase frequency detector ; Phase transitions ; Power efficiency ; quadrature clock corrector ; quadrature phase ; Random access memory ; relaxation oscillator ; Relaxation oscillators</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2019-04, Vol.27 (4), p.978-982</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors. The prototype is implemented in a 55-nm CMOS process with a supply voltage of 1.2 V and occupies an area of 0.003 mm 2 . The experimental results show that the operation range is from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximum duty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phase error is 1.1° at 3 GHz.</description><subject>Capacitors</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Detectors</subject><subject>Digitization</subject><subject>duty cycle</subject><subject>Dynamic random access memory</subject><subject>Dynamic random access memory (DRAM) interface</subject><subject>Frequency conversion</subject><subject>Oscillators</subject><subject>Phase detectors</subject><subject>Phase error</subject><subject>Phase frequency detector</subject><subject>Phase transitions</subject><subject>Power efficiency</subject><subject>quadrature clock corrector</subject><subject>quadrature phase</subject><subject>Random access memory</subject><subject>relaxation oscillator</subject><subject>Relaxation oscillators</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><recordid>eNpNkFtLAzEQhYMoWKt_QF8Cvro1l70kj3XrpVCp1qqPS8xO6Na1W5Ms2Fd_ualbxIFhZuCcM_AhdErJgFIiL-cvk6fxgBEqBkwInnGyh3o0SbJIhtoPO0l5JBglh-jIuSUhNI4l6aHvIX5sVWmVby3gvG70O84ba0H7xmITejQb3uPxyoM1SoO7wK-VX2CFR63fRPlG14DVqvyf8rBQDvAIfBdyFa4SN6vgmUGtvpSvwjF1uqprFQTH6MCo2sHJbvbR8831PL-LJtPbcT6cRJrJxEeaCq4zLojUmYwZTUxGdKwymepYq_JNSsO3EqNiUapECwJQSq6SMjNQxpL30XmXu7bNZwvOF8umtavwsmBUpkIEkjSoWKfStnHOginWtvpQdlNQUmxZF7-siy3rYsc6mM46UwUAfwaRUsKY4D-p7nty</recordid><startdate>20190401</startdate><enddate>20190401</enddate><creator>Chae, Joo-Hyung</creator><creator>Ko, Hyeongjun</creator><creator>Park, Jihwan</creator><creator>Kim, Suhwan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0001-6354-5612</orcidid><orcidid>https://orcid.org/0000-0001-9107-2963</orcidid></search><sort><creationdate>20190401</creationdate><title>A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator</title><author>Chae, Joo-Hyung ; Ko, Hyeongjun ; Park, Jihwan ; Kim, Suhwan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-c183c73809c794215f70c4a796c4cadb99f3183cfa48da5c80eed93a5d7fed493</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Capacitors</topic><topic>Clocks</topic><topic>CMOS</topic><topic>Detectors</topic><topic>Digitization</topic><topic>duty cycle</topic><topic>Dynamic random access memory</topic><topic>Dynamic random access memory (DRAM) interface</topic><topic>Frequency conversion</topic><topic>Oscillators</topic><topic>Phase detectors</topic><topic>Phase error</topic><topic>Phase frequency detector</topic><topic>Phase transitions</topic><topic>Power efficiency</topic><topic>quadrature clock corrector</topic><topic>quadrature phase</topic><topic>Random access memory</topic><topic>relaxation oscillator</topic><topic>Relaxation oscillators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chae, Joo-Hyung</creatorcontrib><creatorcontrib>Ko, Hyeongjun</creatorcontrib><creatorcontrib>Park, Jihwan</creatorcontrib><creatorcontrib>Kim, Suhwan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEL</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chae, Joo-Hyung</au><au>Ko, Hyeongjun</au><au>Park, Jihwan</au><au>Kim, Suhwan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2019-04-01</date><risdate>2019</risdate><volume>27</volume><issue>4</issue><spage>978</spage><epage>982</epage><pages>978-982</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>A quadrature clock corrector uses relaxation oscillators to detect duty-cycle and quadrature phase errors by transforming them into pairs of frequencies, which are then digitized and compared. It achieves good detection accuracy and can detect a wide range of duty-cycle and quadrature phase errors. The prototype is implemented in a 55-nm CMOS process with a supply voltage of 1.2 V and occupies an area of 0.003 mm 2 . The experimental results show that the operation range is from 1 to 3 GHz, the power efficiency is 0.79 mW/GHz, the maximum duty-cycle error is 0.8% at 3 GHz, and the maximum quadrature phase error is 1.1° at 3 GHz.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2018.2883730</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0001-6354-5612</orcidid><orcidid>https://orcid.org/0000-0001-9107-2963</orcidid></addata></record> |
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source | IEEE Xplore (Online service) |
subjects | Capacitors Clocks CMOS Detectors Digitization duty cycle Dynamic random access memory Dynamic random access memory (DRAM) interface Frequency conversion Oscillators Phase detectors Phase error Phase frequency detector Phase transitions Power efficiency quadrature clock corrector quadrature phase Random access memory relaxation oscillator Relaxation oscillators |
title | A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator |
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