Loading…
PUF-Based Secure Chaotic Random Number Generator Design Methodology
Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if...
Saved in:
Published in: | IEEE transactions on very large scale integration (VLSI) systems 2020-07, Vol.28 (7), p.1740-1744 |
---|---|
Main Authors: | , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | cdi_FETCH-LOGICAL-c295t-efc874eddc6a40a317cb91d3976333c2b00ba41574d758081252ce60bc46fca23 |
---|---|
cites | cdi_FETCH-LOGICAL-c295t-efc874eddc6a40a317cb91d3976333c2b00ba41574d758081252ce60bc46fca23 |
container_end_page | 1744 |
container_issue | 7 |
container_start_page | 1740 |
container_title | IEEE transactions on very large scale integration (VLSI) systems |
container_volume | 28 |
creator | Kalanadhabhatta, Srisubha Kumar, Deepak Anumandla, Kiran Kumar Reddy, S. Ashish Acharyya, Amit |
description | Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis. |
doi_str_mv | 10.1109/TVLSI.2020.2979269 |
format | article |
fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1109_TVLSI_2020_2979269</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9046287</ieee_id><sourcerecordid>2418420084</sourcerecordid><originalsourceid>FETCH-LOGICAL-c295t-efc874eddc6a40a317cb91d3976333c2b00ba41574d758081252ce60bc46fca23</originalsourceid><addsrcrecordid>eNo9kE1PwkAQhjdGExH9A3pp4rk4-9Fu96goSIIfEfC62W6nUAJd3G0P_HuLEOfyzuF9ZpKHkFsKA0pBPcy_p7PJgAGDAVNSsVSdkR5NEhmrbs67HVIeZ4zCJbkKYQ1AhVDQI8PPxSh-MgGLaIa29RgNV8Y1lY2-TF24bfTebnP00Rhr9KZxPnrGUC3r6A2blSvcxi331-SiNJuAN6fsk8XoZT58jacf48nwcRpbppImxtJmUmBR2NQIMJxKmytacCVTzrllOUBuBE2kKGSSQUZZwiymkFuRltYw3if3x7s7735aDI1eu9bX3UvNBM0EA8hE12LHlvUuBI-l3vlqa_xeU9AHWfpPlj7I0idZHXR3hCpE_AcUiJRlkv8CCbxknA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2418420084</pqid></control><display><type>article</type><title>PUF-Based Secure Chaotic Random Number Generator Design Methodology</title><source>IEEE Xplore (Online service)</source><creator>Kalanadhabhatta, Srisubha ; Kumar, Deepak ; Anumandla, Kiran Kumar ; Reddy, S. Ashish ; Acharyya, Amit</creator><creatorcontrib>Kalanadhabhatta, Srisubha ; Kumar, Deepak ; Anumandla, Kiran Kumar ; Reddy, S. Ashish ; Acharyya, Amit</creatorcontrib><description>Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2020.2979269</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Chaos ; Chaotic logistic map ; Correlation ; Correlation analysis ; Cryptography ; Field programmable gate arrays ; Generators ; hardware security ; Logic gates ; NIST ; Numbers ; physical unclonable function (PUF) ; Pseudorandom ; pseudorandom number generator (PRNG) ; Random numbers ; Sequences ; Statistical tests</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2020-07, Vol.28 (7), p.1740-1744</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c295t-efc874eddc6a40a317cb91d3976333c2b00ba41574d758081252ce60bc46fca23</citedby><cites>FETCH-LOGICAL-c295t-efc874eddc6a40a317cb91d3976333c2b00ba41574d758081252ce60bc46fca23</cites><orcidid>0000-0002-5636-0676 ; 0000-0002-2067-8711</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9046287$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Kalanadhabhatta, Srisubha</creatorcontrib><creatorcontrib>Kumar, Deepak</creatorcontrib><creatorcontrib>Anumandla, Kiran Kumar</creatorcontrib><creatorcontrib>Reddy, S. Ashish</creatorcontrib><creatorcontrib>Acharyya, Amit</creatorcontrib><title>PUF-Based Secure Chaotic Random Number Generator Design Methodology</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis.</description><subject>Chaos</subject><subject>Chaotic logistic map</subject><subject>Correlation</subject><subject>Correlation analysis</subject><subject>Cryptography</subject><subject>Field programmable gate arrays</subject><subject>Generators</subject><subject>hardware security</subject><subject>Logic gates</subject><subject>NIST</subject><subject>Numbers</subject><subject>physical unclonable function (PUF)</subject><subject>Pseudorandom</subject><subject>pseudorandom number generator (PRNG)</subject><subject>Random numbers</subject><subject>Sequences</subject><subject>Statistical tests</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><recordid>eNo9kE1PwkAQhjdGExH9A3pp4rk4-9Fu96goSIIfEfC62W6nUAJd3G0P_HuLEOfyzuF9ZpKHkFsKA0pBPcy_p7PJgAGDAVNSsVSdkR5NEhmrbs67HVIeZ4zCJbkKYQ1AhVDQI8PPxSh-MgGLaIa29RgNV8Y1lY2-TF24bfTebnP00Rhr9KZxPnrGUC3r6A2blSvcxi331-SiNJuAN6fsk8XoZT58jacf48nwcRpbppImxtJmUmBR2NQIMJxKmytacCVTzrllOUBuBE2kKGSSQUZZwiymkFuRltYw3if3x7s7735aDI1eu9bX3UvNBM0EA8hE12LHlvUuBI-l3vlqa_xeU9AHWfpPlj7I0idZHXR3hCpE_AcUiJRlkv8CCbxknA</recordid><startdate>20200701</startdate><enddate>20200701</enddate><creator>Kalanadhabhatta, Srisubha</creator><creator>Kumar, Deepak</creator><creator>Anumandla, Kiran Kumar</creator><creator>Reddy, S. Ashish</creator><creator>Acharyya, Amit</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-5636-0676</orcidid><orcidid>https://orcid.org/0000-0002-2067-8711</orcidid></search><sort><creationdate>20200701</creationdate><title>PUF-Based Secure Chaotic Random Number Generator Design Methodology</title><author>Kalanadhabhatta, Srisubha ; Kumar, Deepak ; Anumandla, Kiran Kumar ; Reddy, S. Ashish ; Acharyya, Amit</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-efc874eddc6a40a317cb91d3976333c2b00ba41574d758081252ce60bc46fca23</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Chaos</topic><topic>Chaotic logistic map</topic><topic>Correlation</topic><topic>Correlation analysis</topic><topic>Cryptography</topic><topic>Field programmable gate arrays</topic><topic>Generators</topic><topic>hardware security</topic><topic>Logic gates</topic><topic>NIST</topic><topic>Numbers</topic><topic>physical unclonable function (PUF)</topic><topic>Pseudorandom</topic><topic>pseudorandom number generator (PRNG)</topic><topic>Random numbers</topic><topic>Sequences</topic><topic>Statistical tests</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kalanadhabhatta, Srisubha</creatorcontrib><creatorcontrib>Kumar, Deepak</creatorcontrib><creatorcontrib>Anumandla, Kiran Kumar</creatorcontrib><creatorcontrib>Reddy, S. Ashish</creatorcontrib><creatorcontrib>Acharyya, Amit</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kalanadhabhatta, Srisubha</au><au>Kumar, Deepak</au><au>Anumandla, Kiran Kumar</au><au>Reddy, S. Ashish</au><au>Acharyya, Amit</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>PUF-Based Secure Chaotic Random Number Generator Design Methodology</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2020-07-01</date><risdate>2020</risdate><volume>28</volume><issue>7</issue><spage>1740</spage><epage>1744</epage><pages>1740-1744</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2020.2979269</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-5636-0676</orcidid><orcidid>https://orcid.org/0000-0002-2067-8711</orcidid></addata></record> |
fulltext | fulltext |
identifier | ISSN: 1063-8210 |
ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2020-07, Vol.28 (7), p.1740-1744 |
issn | 1063-8210 1557-9999 |
language | eng |
recordid | cdi_crossref_primary_10_1109_TVLSI_2020_2979269 |
source | IEEE Xplore (Online service) |
subjects | Chaos Chaotic logistic map Correlation Correlation analysis Cryptography Field programmable gate arrays Generators hardware security Logic gates NIST Numbers physical unclonable function (PUF) Pseudorandom pseudorandom number generator (PRNG) Random numbers Sequences Statistical tests |
title | PUF-Based Secure Chaotic Random Number Generator Design Methodology |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T11%3A55%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=PUF-Based%20Secure%20Chaotic%20Random%20Number%20Generator%20Design%20Methodology&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Kalanadhabhatta,%20Srisubha&rft.date=2020-07-01&rft.volume=28&rft.issue=7&rft.spage=1740&rft.epage=1744&rft.pages=1740-1744&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2020.2979269&rft_dat=%3Cproquest_cross%3E2418420084%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c295t-efc874eddc6a40a317cb91d3976333c2b00ba41574d758081252ce60bc46fca23%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=2418420084&rft_id=info:pmid/&rft_ieee_id=9046287&rfr_iscdi=true |