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A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain

An simplified vector-sum phase shifter (VSPS) topology is proposed in this article. The proposed VSPS topology employs only one 90° coupler to perform as both an I/Q generator and a vector summer. Compared with the literaturally reported VSPS, the proposed VSPS features a simpler topology and improv...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2022-07, Vol.30 (7), p.966-974
Main Authors: Qiu, Feng, Zhu, Haoshen, Che, Wenquan, Xue, Quan
Format: Article
Language:English
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Summary:An simplified vector-sum phase shifter (VSPS) topology is proposed in this article. The proposed VSPS topology employs only one 90° coupler to perform as both an I/Q generator and a vector summer. Compared with the literaturally reported VSPS, the proposed VSPS features a simpler topology and improved noise figure (NF) performance. Moreover, active baluns based on the self-calibration technique are employed to provide antiphase signals and improve the gain performance of the VSPS. For demonstration, a 24-30-GHz VSPS based on the proposed topology is implemented in the 65-nm CMOS process, exhibiting 3.5° rms phase error and 0.9-dB rms gain error. The average gain of the implemented VSPS is as high as 9 dB at the central frequency of 27 GHz. The NF ranges from 4.8 to 9 dB from 24 to 30 GHz, and the core chip size is 0.36\times0.59 mm 2 .
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2022.3152169