HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2024-03, Vol.32 (3), p.505-518
• Main Authors: Dai, Yuan, Li, Jingyuan, Zhu, Qilong, Qiu, Yunhui, Hu, Yihan, Yin, Wenbo, Wang, Lingli
• Format: Article
• Language: English
• Subjects: Algorithms; Bayesian analysis; Bayesian optimization (BO); coarse-grained reconfigurable architecture (CGRA) mapping; Design optimization; Design parameters; design space exploration (DSE); Energy efficiency; Hardware; Manuals; Modelling; Parameterization; Pipelines; Space exploration; Switches; Synchronism; Synchronization; temporal CGRA; Throughput; Time multiplexing
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2023.3344536

Due to its high energy efficiency and flexibility, coarse-grained reconfigurable architecture (CGRA) has gained increasing attention. Temporal CGRA is a typical category of CGRA that supports single-cycle context switching and time-multiplexing hardware resources to perform spatial and temporal computations. Although multiple temporal CGRAs have been proposed, an architecture with rich design parameters and heterogeneous modeling is still lacking. To this end, we propose a highly parameterized heterogeneous temporal CGRA, called HETA. However, the highly parameterized and heterogeneous design introduces a challenging design space for manual exploration. To address this challenge, we introduce a Bayesian-optimization (BO)-based design space exploration (DSE) of homogeneous and heterogeneous architectures. Different from other DSE processes that require defining the heterogeneous exploration strategy, our approach adopts a searching-pruning-based method without manual intervention. To improve the efficiency of DSE, we develop a fast statistic model for area evaluation, whose error is below 1%. In addition, a pipeline mapping (PiPMap) algorithm is developed to alleviate the restrictions caused by data synchronization and unleash the potential of the proposed architecture. Experimental results show that HETA can achieve 89%, 52%, and 47% improvement in throughput, area efficiency, and energy efficiency over the neighbor-to-neighbor (N2N)-based interconnect CGRA, respectively. Compared with the Switch-based interconnect CGRA, HETA's area efficiency is increased by 61%. Furthermore, compared with the homogeneous architecture of HETA, the optimized heterogeneous architecture improves area efficiency and energy efficiency by 14.7% and 4.8%, respectively.