The extension of self-registered gate and doped-oxide diffusion technology to the fabrication of complementary MOS transistors

• Published in: IEEE transactions on electron devices 1973-05, Vol.20 (5), p.469-473
• Main Authors: Gosney, W.M., Hall, L.H.
• Format: Article
• Language: English
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/T-ED.1973.17675

This paper describes an extension of the well-known self-registered gate PMOS technology for fabricating complementary MOS (CMOS) transistors. Exclusive usage of doped silane oxides as diffusion sources provides accurate and repeatable control of the n-channel-threshold voltage. The use of doped-oxide diffusion sources also makes possible a novel diffusion technique where the n- and p-channel source and drain diffusions can be performed simultaneously with independent control of sheet resistivity. This technique eliminates one high-temperature operation; at the same time, the doped-oxide diffusion sources can be deposited in such a manner as to allow their differing etch rates to provide favorable slopes on the edges of contact windows, a feature that increases yield and reliability. A description of the process is provided along with an electrical characterization of the devices fabricated using this process.