Avalanche breakdown in high-voltage D-MOS devices

A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n + drain contact region. The breakdown is shown t...

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Bibliographic Details
Published in:IEEE transactions on electron devices 1976-01, Vol.23 (1), p.1-4
Main Authors: Declercq, M.J., Plummer, J.D.
Format: Article
Language:English
Subjects:
Avalanche breakdown
Breakdown voltage
Doping
Electric fields
Logic gates
Transistors
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Summary:A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n + drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n + region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.
ISSN:0018-9383
1557-9646
DOI:10.1109/T-ED.1976.18337