50 nm gate electrode patterning using a neutral-beam etching system

A 50-nm-width metal-oxide-semiconductor (MOS) gate etching process was established using a recently-developed neutral-beam etching system by optimizing the gas chemistry and the electrode bias condition. In a comparison with poly-Si gate etching using either SF 6 or Cl 2 gas chemistries, opposite et...

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Bibliographic Details
Published in:Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films Surfaces, and Films, 2004-07, Vol.22 (4), p.1506-1512
Main Authors: Noda, Shuichi, Nishimori, Hirotomo, Ida, Tohru, Arikado, Tsunetoshi, Ichiki, Katsunori, Ozaki, Takuya, Samukawa, Seiji
Format: Article
Language:English
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Summary:A 50-nm-width metal-oxide-semiconductor (MOS) gate etching process was established using a recently-developed neutral-beam etching system by optimizing the gas chemistry and the electrode bias condition. In a comparison with poly-Si gate etching using either SF 6 or Cl 2 gas chemistries, opposite etching characteristics were observed in the pattern profile. Consequently, the use of a mixture of these gases was proposed in order to achieve fine control of the etching profiles. The energy of the neutral beam was increased by applying a 600 kHz rf bias to the bottom electrode. The rf bias was very effective in increasing the etch rate and the anisotropy of the poly-Si gates, with no deterioration of the neutralization efficiency. The oxide leakage current achieved for a MOS capacitor etched by the neutral beam was one order of magnitude lower than that achieved by conventional plasma etching.
ISSN:0734-2101
1520-8559
DOI:10.1116/1.1723338