Compliant pin chuck for minimizing the effect of backside particles on wafer planarity

• Published in: Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 2004-11, Vol.22 (6), p.3147-3150
• Main Authors: Nimmakayala, Pawan Kumar, Sreenivasan, S. V.
• Format: Article
• Language: English
• ISSN: 0734-211X; 1071-1023; 1520-8567
• DOI: 10.1116/1.1825017

A wafer chuck referred to as the compliant pin chuck (CPC) that can minimize the nonplanarity effect of backside particles on semiconductor wafers is presented in this article. The demand for flatter semiconductor substrates has been increasing as the size of the features that can be transferred onto a wafer surface becomes smaller. There are a number of factors affecting wafer planarity, most of which can be corrected by conventional wafer chucks. However, the problem of backside particles (particles affect a large portion of wafer real estate by causing out-of-plane distortion when they get lodged between a wafer and a wafer chuck) has not been adequately addressed by the current wafer chuck technology. The compliant pin chuck was designed to address this concern and fabricated from silicon using lithography based microfabrication techniques. The chuck consists of an array of microflexure mechanisms that react to the presence of backside particles so as to minimize the nonplanarity caused otherwise. It is also shown through experimental results that the fabricated chuck has a planarity of 120 nm (standard deviation − 3 σ ) over an area of 30 mm × 30 mm and is less sensitive to backside particles than a conventional wafer chuck.