Sub-10 ps Logic Operations in Josephson Four-Junction Logic (4JL) Gates

Sub-10 ps logic delays have been obtained in a Josephson four junction logic (4JL) gate. An experimental circuit including a logic chain of ten 4JL gates whose minimum junction size is 2.5 µm square has been fabricated using a Pb-alloy integration technology. The shortest switching delay has been me...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 1983-05, Vol.22 (5A), p.L297
Main Authors: Nakagawa, Hiroshi, Odake, Takeshi, Sogawa, Eiichi, Takada, Susumu, Hayakawa, Hisao
Format: Article
Language:English
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Summary:Sub-10 ps logic delays have been obtained in a Josephson four junction logic (4JL) gate. An experimental circuit including a logic chain of ten 4JL gates whose minimum junction size is 2.5 µm square has been fabricated using a Pb-alloy integration technology. The shortest switching delay has been measured to be 7 ps/gate for the fanout of 1 with a power dissipation of 4 µW/gate.
ISSN:0021-4922
1347-4065
DOI:10.1143/JJAP.22.L297