Identification of grain-boundary trap properties using three-level charge-pumping technique in polysilicon thin-film transistors

The grain-boundary trap properties in polysilicon thin film transistors (poly-Si TFTs) are evaluated using the three-level charge-pumping (3CP) technique. By measuring the 3CP current with various fall times, we can obtain the grain-boundary trap distribution for each time constant window. The 3CP c...

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Bibliographic Details
Published in:Japanese Journal of Applied Physics 1997-03, Vol.36 (3B), p.1394-1397
Main Authors: KIM, K.-J, KIM, O
Format: Article
Language:English
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
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Summary:The grain-boundary trap properties in polysilicon thin film transistors (poly-Si TFTs) are evaluated using the three-level charge-pumping (3CP) technique. By measuring the 3CP current with various fall times, we can obtain the grain-boundary trap distribution for each time constant window. The 3CP current versus step voltage characteristics indicate that the total change of 3CP currents drastically increase as the fall time decreases and as the step time increases. The large change of 3CP current indicates that a large number of grain-boundary traps ( D gb ≥4 ×10 11 eV -1 ·cm -2 ) exist in the upper half of the band gap in the n-channel TFTs. The grain-boundary trap density is derived from the step voltage dependence of the 3CP current. The influence of process temperature on trap properties is examined using the 3CP technique.
ISSN:0021-4922
1347-4065
DOI:10.1143/JJAP.36.1394