Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture

• Published in: Japanese Journal of Applied Physics 2005-04, Vol.44 (4S), p.2083
• Main Authors: Lee, Kung-Hong, Wu, Meng-Yi, Dai, Sen-Hue, King, Ya-Chin
• Format: Article
• Language: English
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.44.2083

A novel flash memory cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process and its corresponding array architecture is presented. The cell which consists of two metal-oxide-semiconductor field effect transistors (MOSFET) in series is programmed by channel current induced drain avalanche hot hole and erased by channel hot electron injection. With novel operation principles and array architecture, a feature-sized n-MOSFET per non-volatile memory bit is successfully demonstrated and the CMOS-process-based flash cell size can be as small as multi-gated flash memory. The smallest bit area of a CMOS-process-based flash memory cell with good programming and erasing characteristics along with endurance up to 10 5 cycles, 10 years excellent read disturbance and data retention characteristics of data retention at 150°C is proposed. With its small cell size and full compatibility with standard CMOS logic process, the novel flash memory cell can be easily adapted in highly integrated very large scale integration (VLSI) systems.