Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

• Published in: Japanese Journal of Applied Physics 2005-04, Vol.44 (4S), p.2157
• Main Authors: Hayashi, Takashi, Yamashita, Tomohiro, Shiga, Katsuya, Hayashi, Kiyoshi, Oda, Hidekazu, Eimori, Takahisa, Inuishi, Masahide, Ohji, Yuzuru
• Format: Article
• Language: English
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.44.2157

Boron penetration from the poly-silicon gate to the silicon substrate through gate dielectrics is a crucial problem in the dual gate complementary metal-oxide semiconductor (CMOS) process. Therefore, the plasma nitridation technique has been studied well, and it has succeeded to suppress boron penetration. However, boron penetration occurs not only from the doped poly-silicon gate but also from the substrate, and resulting in several degradations of gate-oxide characteristics. On the other hand, the boron concentration of source/drain (S/D) extension has been increasing with gate shrinkage. We found that boron penetration from the S/D extension becomes a crucial problem in gate leakage and gate-oxide integrity, particularly for nanoscale positive-channel MOS (pMOS). In this study, we examined several treatments in detail to suppress boron penetration from the S/D extension, and demonstrated that the plasma nitridation treatment after gate etching is the best solution for 65-nm node CMOS and beyond.